Projects
Title: Low-Power 32 GT/s x32 Advanced-Package UCIe PHY for Die-to-Die Interface
Role: Digital Designer
Organization: Samsung Electronics
Designed RTL and digital architecture for a high-speed UCIe PHY, including Link Training State Machine (LTSM) logic, PHY initialization/training flow, APB-based register access and control, and digital frontend implementation such as RTL simulation, lint, CDC analysis, synthesis, and timing-closure.
Title: Custom MCU for High-Speed PHY Post-Silicon Validation
Role: Digital Designer
Application: 64 GT/s x64 Advanced-Package UCIe PHY
Organization: Samsung Electronics
Designed a custom MCU integrated with the IP to improve flexibility, testability, and debuggability. Defined the opcode set and instruction behavior, and architected the MCU for small memory usage. Integrated the MCU into an IP and built a dedicated compiler to support post-silicon validation on ATE and enable rapid bug fixes through software code.
Title: LazyVerilog
Languages: C++
Repository: github.com/kjoonha/LazyVerilog
LazyVerilog is a open-source SystemVerilog LSP for RTL coding. It provides formatting, lint diagnostics, go-to-definition, references, rename, hover, completion, inlay hints, RTL tree navigation, and RTL code actions such as auto-instantiation, auto-wire, and auto-arg.
Title: Integer-N ADPLL with Proportional and Integral Gain Co-Optimization Technique
Technology: Samsung 28nm
Clock Frequency: fref = 100MHz, fout = 3.2GHz
Designer: Kyoungjoon Ha
